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IEEE International High-Level Design, Validation and Test Workshop (HLDVT'05)
Nov. 30 - Dec. 2, 2005
Napa Valley Marriott Hotel & Spa
Napa, California

http://www.hldvt.com/05

CALL FOR PAPERS

Overview -- Paper Submissions -- Contacts

Overview

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HLDVT 2005 is the tenth in a series of annual workshops designed to bring together a community of researchers in the areas of design, verification, and test. The workshop revolves around a common theme of addressing the integration of multiple functions on-chip at higher levels of design abstraction, and the techniques and methodologies for modeling, analyzing, and validating such systems. Topics include:

  • High-Level Power Analysis
  • Behavioral Design/Synthesis for Test
  • Testing Core-Based Designs
  • Simulation-Based Validation
  • Emulation and Prototyping
  • System-Level Design Error Modeling
  • Hardware/Software Co-Validation
  • High-Level Performance Models
  • High-Level ATPG/Fault Simulation
  • On-Chip Software Testing
  • Formal Verification
  • High-Level Test Bench Generation
  • Error Debug and Diagnosis
  • Hardware/Software Co-Testing

Paper Submissions

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The Program Committee invites authors to submit papers not to exceed 8 pages (10pt minimum font size, reasonable margins and line spacing) describing original and unpublished work. On the title page, please indicate: paper title, name and affiliations of all authors, and the topic category. Also identify a contact author and provide complete mailing address, phone number, fax number and an e-mail address. Panel proposals are also invited. All submissions must be made electronically in PDF or Postscript format using the paper submission webpage:

http://www.hldvt.com/submissions

Please ensure that your PDF or Postscript file is readable by Acrobat Reader or Ghostview. The submission of an extended summary or panel proposal will be considered evidence that upon acceptance, the author(s) will present their paper or organize their panel at the workshop. The final manuscript will be due in early September 2005.

Submission deadlines: July 8, 2005 (notification on August 12, 2005)

Contacts

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Additional information and contact addresses are available at the conference website:

http://www.hldvt.com/05

Queries regarding paper submissions and the program can be addressed to the program chair: Robert Jones, programchair@hldvt.com. Other queries can be addressed to the general chair: Ian Harris, generalchair@hldvt.com.

For more information, visit us on the web at: http://www.hldvt.com/05

The International High-Level Design, Validation and Test Workshop (HLDVT'05) is sponsored by the Institute of Electrical and Electronics Engineers (IEEE) Computer Society's Test Technology Technical Council (TTTC) and the IEEE Computer Society Design Automation Technical Committee.


IEEE Computer Society - Test Technology Technical Council

TTTC CHAIR
André IVANOV
University of British Columbia - Canada
Tel. +1-604-822-6936
E-mail ivanov@ece.ubc.ca

SENIOR PAST CHAIR
Yervant ZORIAN
Virage Logic - USA
Tel. +1-510-360-8035
E-mail yervant.zorian@viragelogic.com


TTTC 2ND VICE CHAIR
Michel RENOVELL
LIRMM - France
Tel. +33 467 418 523
E-mail renovell@lirmm.fr

FINANCE CHAIR
Adit D. SINGH
Auburn University - USA
Tel. +1-334-844-1847
E-mail adsingh@eng.auburn.edu

IEEE DESIGN & TEST EIC
Rajesh K. GUPTA
University of California, Irvine - USA
Tel. +1-949-824-8052
E-mail gupta@uci.edu

TECHNICAL MEETINGS
Cheng-Wen WU

National Tsing Hua Univ. - Taiwan
Tel. +886-3-573-1154
E-mail cww@computer.org

TECHNICAL ACTIVITIES
Victor Hugo CHAMPAC
Instituto Nacional de Astrofisica - Mexico
Tel.+52-22-470-517
E-mail champac@inaoep.mx

ASIA & SOUTH PACIFIC
Hideo FUJIWARA
Nara Inst. of Science and Technology - Japan
Tel. +81-74-372-5220
E-mail fujiwara@is.aist-nara.ac.jp

LATIN AMERICA
Marcelo LUBASZEWSKI
Federal Univ. of Rio Grande do Sul (UFRGS) - Brazil
Tel. +34-93-401-6603
E-mail luba@vortex.ufrgs.br

NORTH AMERICA
William R. MANN
Tel. +1-949-645-3294
E-mail william.mann@ieee.org

COMMUNICATIONS
Adit D. SINGH
Auburn University - USA
Tel. +1-334-844-1847
E-mail adsingh@eng.auburn.edu

INDUSTRY ADVISORY BOARD
Yervant ZORIAN
Virage Logic, Inc. - USA
Tel. +1-510-360-8035
E-mail yervant.zorian@viragelogic.com

 

PAST CHAIR
Paolo PRINETTO
Politecnico di Torino - Italy
Tel. +39-011-564-7007
E-mail Paolo.Prinetto@polito.it

TTTC 1ST VICE CHAIR
Adit D. SINGH
Auburn University - USA
Tel. +1-334-844-1847
E-mail adsingh@eng.auburn.edu

SECRETARY
Christian LANDRAULT
LIRMM - France
Tel. +33-4-674-18524
E-mail landrault@lirmm.fr

ITC GENERAL CHAIR
Rob AITKEN
Artisan Components - USA
Tel. +1-408-548-3297
E-mail aitken@artisan.com

TEST WEEK COORDINATOR
Yervant ZORIAN
Virage Logic, Inc. - USA
Tel. +1-510-360-8035
E-mail yervant.zorian@viragelogic.com

TUTORIALS AND EDUCATION
Dimitris GIZOPOULOS

Univ. of Piraeus - Greece
Tel. +30-210-414-2372
E-mail dgizop@unipi.gr

STANDARDS
Rohit KAPUR

Synopsys - USA
Tel. +1-650-934-1487
E-mail rkapur@synopsys.com

EUROPE
Joan FIGUERAS
Univ. Politècnica de Catalunya - Spain
Tel. +55-51-228-1633, Ext. 4830
E-mail figueras@eel.upc.es

MIDDLE EAST & AFRICA
Ibrahim HAJJ
American University of Beirut - Lebanon
Tel. +961-1-341-952
E-mail ihajj@aub.edu.lb

STANDING COMMITTEES
Michael NICOLAIDIS
iRoC Technologies - Greece
Tel. +33-4-381-20763
E-mail michael.nicolaidis@iroctech.com

ELECTRONIC MEDIA
Alfredo BENSO
Politecnico di Torino - Italy
Tel. +39-011-564-7080
E-mail alfredo.benso@polito.it


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